1) Field of Invention
The present invention relates in general to non-volatile semiconductor memories, and more particularly relates to erasable read-only memory devices, and methods of fabrication thereof.
2) Description of Prior Art
A shortcoming of conventional EPROM cells is the low gate coupling ratio. Conventional electrically programmable read-only memory (EPROM) cells typically have control gates that overlie the top or the top and sides of floating gates. When a control gate overlies only the top of the floating gate member, the capacitive coupling between the floating gate member and control gate member typically does not exceed about 50% of the floating gate capacitance (i.e., capacitance ratio=50%). When a control gate lies adjacent to the top and sides of the floating gate the capacitance coupling ratio may increase to about 70%.
An attempt to increase capacitive coupling ratio may include the use of a control gate that lies adjacent to the top, sides, and part of the bottom of a T-shaped floating gate. The formation of this type of device is complex and may include two deposition steps and two patterning steps. Further, the intergate dielectric layer (between the control gate and the floating gate) may include two distinct regions, and its formation may require three steps. For example, one region may be between the bottom of the floating gate and an underlying portion of the control gate, and the other region may be between the top of the floating gate and an overlying portion of the control gate. Extra processing steps typically lower yield, raise substrate cost, increase cycle time, and are generally undesired.
A major shortcoming with conventional methods of forming floating gates is the low gate coupling ratios which reduce the bias in writing or programming in Flash EPROM's.
There is a need for an improved method of forming a floating gate with a higher gate coupling ratio. There is a need to form a gate with a larger surface area.
The most pertinent patents in the art are U.S. Pat. No. 5,141,891 (Arima et al.) and 4,892,840 (Esquival et al.) which show an EPROM with a "U" shaped floating and control gates. U.S. Pat. No. 5,543,339 (Roth et al.) shows a EPROM having U shaped electrode. U.S. Pat. No. 5,583,066 (Jung) shows a well shaped floating gate surrounding a control gate.